1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Related Art
In recent years, size reduction of an element such as an active element formed over a semiconductor substrate has been advanced with increase in an integration scale of a semiconductor integrated circuit. Meanwhile, despite improvement of performance of an element with its size reduction, wirings for connecting the elements are difficult to be narrowed in accordance with the size reduction, because of restrictions on current density and the like. In order to solve this problem, a multilayer structure has been employed in which active elements are connected by forming a plurality of wiring layers. In particular, in an integrated circuit for a specific purpose such as a gate array (ASIC: Application Specific Integrated Circuit) as a structure for increasing the number of wiring layers, the number of wiring layers reaches as many as five or six. Accordingly, the number of connections between the respective elements and wirings and between the overlapping wiring layers becomes extremely large.
On the other hand, since there is a demand of improving performance and decreasing power consumption of a large-scale integrated circuit (LSI) as well as reducing a wiring width, it is necessary to lower the height of a wiring so as to decrease a capacitance between the wirings within the same wiring layer. Consequently, it has been examined to use a wiring material having low electric resistance and high electromigration resistance, that is, high allowable current density, such as copper. In the case of using copper which has low electric resistance so as to increase the allowable current density, an embedded wiring obtained by a chemical mechanical polishing (hereinafter referred to as CMP) technique of metal is suggested because copper itself is difficult to process. Specifically, a dual damascene method is given. According to the dual damascene method, a wiring leading portion and a plug portion can be simultaneously formed with one conductive film by embedding the conductive film in a contact hole for electrically connecting an upper wiring and a lower wiring at the time when the wiring is embedded in an interlayer insulating film.
In another technique for decreasing the capacitance between the wirings, a low dielectric constant material is used for an interlayer film. There are many known combinations of a low dielectric constant material with the dual damascene method. Above all, a technique in which a porous material is used as a dielectric material has been proposed and examined extensively to achieve the decrease in delay due to the wiring resistance and the wiring capacitance (see Non-Patent Document 1: Nikkei Microdevices (Nikkei Business Publications, Inc.), pp. 58 to 65, November, 2004). A porous material having a siloxane bond, such as a porous silica material is mainly examined, and the general composition is SiOxCyHz.
An ideal porous low dielectric constant film has a structure in which air holes (also referred to as airspaces or pores) each of which is independent and has a diameter of 1 to 2 nm distribute uniformly in the film. As a method to achieve this structure, a technique by spin coating and baking is given. As a forming method by spin coating, such a method is examined that a polymer material which evaporates at a certain temperature is mixed into a porous material and these are evaporated through a heat treatment so that air holes are formed in an insulating film.
As for an example of a dual damascene method using SiLK (registered trademark) as a low dielectric constant material, Patent Document 1 (U.S. Pat. No. 6,383,920) may be referred to.
However, in order to decrease the dielectric constant of the porous insulating film to be typically less than 2.5, the pore ratio of the insulating film is preferably 30% or more. However, as the pore ratio gets higher, the mechanical strength of the insulating film becomes lower, which causes a problem in that the insulating film may be ground excessively or a conductive film for forming a wiring may be peeled off in a CMP process.
Moreover, in a conventional dual damascene process, it is necessary to fill a contact hole with a conductive film so that even a bottom portion of the contact hole is filled because the formation of a wiring and the filling of the contact hole are conducted at the same time. Therefore, the conductive film is embedded into the connection hole and a wiring groove by conducting a reflow process to the conductive film. However, the conductive film cannot be completely embedded into an interlayer insulating film having a dual damascene structure with an opening having an aspect ratio of approximately 4 to 5, causing a problem in that a void or a coverage defect portion is easily formed in the connection hole and the wiring groove to decrease the yield.
Moreover, a large number of steps are required to form a wiring having a dual damascene structure, which includes a step of etching to form a connection hole and a wiring groove, a step of electroplating copper, a CMP step, and the like. Therefore, throughput has decreased, and economical and environmental problems due to the low throughput were caused.
Furthermore, a dual damascene process includes a polishing step. Therefore, in steps of manufacturing semiconductor elements such as display devices over a large substrate, the degree of the polishing is likely to vary. This makes it difficult to manufacture a semiconductor device with a high yield because some problems occur in which the wirings short out, the thicknesses of the wirings vary, and so on.